It should be easier to do in software. What's hard is, modelling the hardware accurately, getting the timing correct, AND getting everything performant enough to run at the original hardware speeds. It takes a beefy system to accurately emulate even SNES hardware at full speed. An FPGA can be programmed with accurate hardware models and run them all in parallel at the same speeds the original hardware ran at (up to a limit, I believe today it's somewhere in the low hundreds of MHz for a CPU). This allows for a closer approximation of the original hardware running at usable speeds.
It used to take a beefy system to emulate the SNES at full speed. Emulator performance has improved, CPU performance has improved, and nowadays, an outdated and low-spec x86 laptop will run BSNES.
You will have problems running BSNES on a Raspberry Pi, though, although I've heard the RPi 4 can do it.
Moreover, it can actually be at least "more straightforward" to reach accurate wall clock timings with an FPGA, than by trying to meet deadlines in a common OS environment, as the FPGA is "just" loaded with a bitstream that will it do more or less exactly what the original chip did and nothing else, spoken strictly in the digital domain.
I'd also like to think that it's more efficient, since at least in theory it could be (cutting down on all the extremely superfluous software overhead for the task), but sadly I don't actually know how common FPGAs really perform in that specific case against reasonably efficient modern CPUs.
