Semiconductor industry has the deepest and most complex value chain in the economy.
TSMC has always been pure fab company and it pays off now. Samsung and Intel are also in chip design business and do other things. They are less focused. TSMC's lead is not guaranteed. Any new technology node can fail and remove them from competition if they make wrong choices.
I'm not exaggerating when I say that designing a new technology node for mass production is like a moon program. TSMC designs new node every few years, builds a fabs that cost 20+ billion. ASML machines are the most expensive tooling there but they are just part of the whole.
Intel and Samsung are almost as good, but small differences have huge impact in the final result and timing. Small percentages in final yield can make a difference.
A bit of an aside, but your comment made me realize how much we don’t know about the process used to create the technologies that underpin our civilization.
We (laymen) have no idea about the incredible complexity behind manufacturing a single CPU chip.
> we don’t know about the process used to create the technologies that underpin our civilization.
It's been like that for a while. That's why we need everyone else to function as a society.
I've watched a couple blacksmithing videos on youtube but I still don't really know how smelting iron works, and I wouldn't be able to produce a steel if my life depended on it. That's literally 2500+ year old tech.
It was science back then, it is science now. Using technologies at the time. 2000 years from now, some people will look at our era as barbarian and unscientific.
Many years ago I sat next to the CTO of Broadcom on a plane. We struck up a conversation and when I learned he worked for a chip designer I asked the question that I assumed was the most difficult part. I asked how the engineers laid out the circuits physically on the chip. He laughed and told me the engineers write software that defines the parameters and functions and the software lays out the chip (I know I am oversimplifying). I was dumbfounded to learn that hardware design was really software development. Today I think Google has an open chip design effort where you write chip specs in Python (from memory).
They even have their own languages for coding the chip logic ( Verilog is one).
My partner did chip design and layout. The used a tool call magma (We have some mugs from a conference she went to) but they got bought by synopsis. Very expensive, very specialized software
This was probably not true many years ago, or at least was a simplification. Even with some automated routing, there are many subtleties like high frequency electronics; not trying to have your radio equipment routing through your power supply, etc.
It is a mix: digital logic is almost entirely laid out by machine, but analog circuits and the underlying logic cells (as well as certain specialised digital blocks like memories) are a lot less automated. The most expensive part isn't doing that: it's doing the validation and simulation of the design so that it'll have the best chance of working after you've spend 5-6 figures and many months on actually building it (and then there's the cost of testing it in reality and figuring out what isn't actually working and how to fix it: the first batch of chips still extremely rarely works).
Most people don't even know where their water comes from. Most people that drive do not know how a combustion engine works. Even people watching TV are only vaguely aware it's a series of static images chained together to make it look like its moving.
People in general have a barely functional understanding of computing devices, let alone their operating systems or hardware components, at an usage level.
Their fabrication process is so far removed that I don't think most people would even be able to know where to look for the information, even if they could access and understand all of it.
That also reminded me of _Connections_, which notably made the same point in _the late 1970s_! It isn't like technology's gotten any easier to understand -- in total, "top to bottom" -- since then.
What is a node in this context and what does designing a new node entail? Does this design process mean TSMC can do something with ASML machines that another company with the same machine couldn't do?
The important thing to understand is that at the level of chip manufacturing, you’re doing advanced materials science. These aren’t just abstract logic gates and structures built out of them, such as SRAMs. At the manufacturing level, the logic gates are nano-scale 3D structures made of different materials and in different shapes. For example, at this scale, the shape of the transistor gates has a big effect on performance: https://en.wikipedia.org/wiki/Fin_field-effect_transistor. That materials science is highly guarded secret sauce in companies like TSMC. NVIDIA and Apple will tell TSMC what logic gates go where (or often at an even higher level—specifying certain SRAM blocks going here or there). But TSMC has to actually build the nano-scale material structures that comprise those logic gates.
The ASML machines perform the actual photolithography. They expose the die mask to the photoresist coated silicon wafer. Using that technique, you can built up complex 3D materials incorporating different layers and shapes. But the ASML machine doesn’t know how to make a transistor. It’s kind of like a 3D printer in that way.
> NVIDIA and Apple will tell TSMC what logic gates go where (or often at an even higher level—specifying certain SRAM blocks going here or there).
That's not quite how design works; it's much much more detailed. At the end of the day, TSMC's customers send them a "GDS" file that is a complete physical representation of the die they want manufactured. It describes every top-to-bottom later of the manufacturing process. (TSMC will take the GDS layers and split them up or combine them or do other operations, depending on some process details, but the customer will also check and sign off on that).
It's not just telling TSMC where to put standard cells or SRAM. And while TSMC does offer their own standard cells and SRAM, customers can and often do design and use their own. Analog/RF design is even more detailed, since that's done at an individual transistor level.
TSMC is mainly in the business of design and selling a manufacturing process for making transistors not logic gates.
I was under the impression that it’s unusual for fabless chipmakers to do transistor level design anymore, and that they mostly rely on the standard TSMC libraries. But I may be wrong about that. The critical point I was trying to make is that the ASML machine doesn’t know how to make transistors. That’s something TSMC does: https://www.anandtech.com/show/16041/where-are-my-gaafets-ts...
No that's definitely not the case. For digital design, in general, you're not doing anything transistor-level. But those digital designers are using standard cell or memory libraries which are created at a transistor level. I believe the foundries also charge for their own standard cell libraries, and there are many other vendors that a design company can choose from like cadence, synopsys, even ARM.
For analog/RF design, of which there is still an enormous amount, it's always transistor level.
Theoretically, yes, but in practice, no. Creating a manufacturing process is a very complex and time consuming process that takes a huge about of research and development, investment, etc to achieve profitable yields. For bulk CMOS processes, which is what digital circuits are made on, this is especially the case. Foundries like TSMC can't afford to let customers design custom transistors, and customers generally don't have the expertise to do so. There's a huge economies of scale benefit from having customers all use the same process.
That being said, there is a little room for tweaking. The manufacturing process has a ton of variation in it, and the center point / average of that variation can be moved around a little. I think most companies just take what they get, but I'm betting the big players (Qualcomm, Apple, Nvidia, AMD) all do internal tracking of the process variation when they get product back, and give feedback to the foundries to make changes to optimize their own yield.
There's also been a recent push in the very new and advanced processes for "Design-Technology Co-Optimization", where the digital circuit design (i.e. standard cells and memory) and the process technology design happens together. We got here because all of the low hanging fruit has been picked and now companies are chasing single digit percentages in yield and PPA (power, performance, and area) improvements. It's a collaboration between foundry and customer that happens before the process is even released, so again - big players only, and it's still more tweaking than custom transistors.
For other types of processes, meaning non-bulk CMOS, customers can definitely design their own transistors. This is especially common in RF applications where you're often making chips with a few transistors. In some cases, it can be just changes in the shapes and/or dimensions of the transistors in the GDS, relative to what the foundry recommends. For this type of custom transistor, the foundry still controls the material science details of how the process happens. In other cases, though, customers are in control of everything from the transistor dimensions to the chemical concentrations and methods used for fabrication.
So in that case there is no materials secret sauce guarded by TSMC, with the customer either submitting the GDS file with all the info, or signing off on the modified version.
Sorry my comment wasn't very clear about this. There's still secret sauce in the materials. The GDS is purely dimensional. It's just a bunch of shapes. But how those shapes get translated into actual silicon, and how various chemicals are used and in what concentrations to manipulate the silicon to make the transistors function is the secret sauce.
It's also important to note how crazy the ASML EUV machines are, they each take a megawatt of power to produce about 100 watts of EUV. The infrastructure just to run these machines is staggering. TSMC uses about 5% of Taiwans total power I believe.
I like you 3d printing reference. You can have 2 people with the same printer trying to print the same part. What else goes into getting a good part? Proper bed leveling, bed heating, choice of material, part cooler, nozzle temperature, feed rate, speed, acceleration, layer thickness, infill pattern, and many other settings and choices. And that's just an off the shelf printer melting plastic...
Ya this analogy really clicked with me. To really torture the analogy, Apple or any other TSMC customers hands them an .obj of their chip, and TSMC acts as the slicer and converts that into the GCode that ASML’s “printers” understand. And just like how some slicers have better overhang and infill algorithms TSMC has their own secret sauce for telling the ASML machines what to “print”.
Does that expansion of the analogy work or did I just move the analogy further from the truth?
It's a good analogy but there's one more major aspect. The silicon wafer doesn't sit under a single "printer" the whole time. It has to be moved around between countless different machines all doing different specialized tasks. So there is a huge logistical challenge as well. It is like combining 3D printing with an international airline.
This might be pedantic nit-picking, but: I think bed leveling/heating, nozzle temperature, choice of material, etc. are parameters that the printer manufacturer should have optimized (and, IME, good ones do). I think the end user's chief responsibility is slicing (infill patterns, layer thickness, etc. as you noted), indeed it is in this sense the end user can be said to be in the same position as Intel/Samsung, not so much the hardware maintenance but knowing the slicing tricks for getting complicated geometry to come out just right.
For example, when you're making a cube, the sharp ends are places where bad things happen. When making sharp movements, the nozzle will tend to leave ugly trails and in other times cause warping. So here you can do a trick to save yourself: mouse-ears (extra material around the important edge, so that the bad artifacts happen instead on additionally-created non-core-geometry). At ground level, you use brims.
The interview that I posted above discusses copper interconnects that IBM research introduced.
TSMC had previously used a "spin-on" dialectic technique at a previous node, and reverted to CVD because of problems.
They were able to beat all other manufacturers to market with copper interconnects (including IBM), because they avoided spin-on, which worked well in testing, but not in production.
They had great luck in gaining this prior experience.
>I'm not exaggerating when I say that designing a new technology node for mass production is like a moon program.
It's insane. I had a friend tell me about what goes on in these asml machines. Essentially the targeting system that moves the wafer around cannot have any vibration so I kid you not the platform is floating and controlled by magnets. And this is just the etching machine.
The etching process that uses a laser to blast a moving molten tin sphere to shape it so the next laser blast that vaporizes it produces parallel EUV light is pretty insane, too. See https://www.youtube.com/watch?v=5Ge2RcvDlgw
I worked on a campus where they were building prototype manufacturing processes with these tools.
The building those tools were housed in had a foundation that was iirc 30’ of a specialized concrete mix. I was chatting with some of the construction engineers over coffee and the consensus was that 10,000 years from now, some archeologists would be pondering wtf this giant concrete platform was for.
TSMC has always been pure fab company and it pays off now. Samsung and Intel are also in chip design business and do other things. They are less focused. TSMC's lead is not guaranteed. Any new technology node can fail and remove them from competition if they make wrong choices.
I'm not exaggerating when I say that designing a new technology node for mass production is like a moon program. TSMC designs new node every few years, builds a fabs that cost 20+ billion. ASML machines are the most expensive tooling there but they are just part of the whole.
Intel and Samsung are almost as good, but small differences have huge impact in the final result and timing. Small percentages in final yield can make a difference.