> I think an example is something like opcodes crossing I-cache lines Consider a...

		rsaxvc on Oct 24, 2023 \| parent \| context \| favorite \| on: The risk of RISC-V: What's going on at SiFive? > I think an example is something like opcodes crossing I-cache lines Consider also a 16-bit aligned 32-bit instruction crossing a page boundary, potentially with different access permissions. This type of bug allowed userspace applications to hang early Cortex-A8 based phones(ARM errata 657417).

See also: Intel SKX102, whose documentation has nice diagrams.