> I would definitely like to see if the x86 industry could figure out how to include more channels while also not requiring 6-8 DIMMS to take advantage of it, like Thread Ripper.
you can't really do that, DDR5 has a concept called "pseudo-channels" where a normal 64b channel can be broken down into 2x32 smaller ones, which improves parallel efficiency somewhat (now you can have 2 requests in-flight at the same time). But mostly bandwidth is down to the number of pins and how much data you can physically push down them, chopping the same pins into smaller channels doesn't help, other than letting you eliminate some inefficiency/overhead.
however, this is essentially the goal behind strix point/strix halo - narrower memory buses (compared to apple) with cache to improve the effective bandwidth. Just like in GPUs, this allows you to use fewer channels to get to the same bandwidth, which means less actual data movement. The downside is, of course, less "raw" bandwidth, if your workload is not cacheable.
basically my rough expectation is that it's going to be more expensive than apple silicon, and still probably not actually beat on power, but will allow you to do workstation laptops with 512GB or 1TB of unified memory, which is also something the apple stuff cannot do. They are different products, apple is targeting people who want a powerful ultrabook, amd is targeting people who want a mobile threadripper for actual work tasks (metrology is one example).
you can't really do that, DDR5 has a concept called "pseudo-channels" where a normal 64b channel can be broken down into 2x32 smaller ones, which improves parallel efficiency somewhat (now you can have 2 requests in-flight at the same time). But mostly bandwidth is down to the number of pins and how much data you can physically push down them, chopping the same pins into smaller channels doesn't help, other than letting you eliminate some inefficiency/overhead.
however, this is essentially the goal behind strix point/strix halo - narrower memory buses (compared to apple) with cache to improve the effective bandwidth. Just like in GPUs, this allows you to use fewer channels to get to the same bandwidth, which means less actual data movement. The downside is, of course, less "raw" bandwidth, if your workload is not cacheable.
basically my rough expectation is that it's going to be more expensive than apple silicon, and still probably not actually beat on power, but will allow you to do workstation laptops with 512GB or 1TB of unified memory, which is also something the apple stuff cannot do. They are different products, apple is targeting people who want a powerful ultrabook, amd is targeting people who want a mobile threadripper for actual work tasks (metrology is one example).