> What I'd be more interested in is, does this also mean bigger/denser L1-L3 caches?
Just a semi-engineer here, not a semi-conductor engineer, but probably not. L1-L3 are on the die, so you'd just be making those at the same time as the rest of your CPU die, so they'll be made with the same process as that is. Which, once that process is the high NA UV, means yes, denser L1-L3. Though I wouldn't be too surprised to see an L3/L4 chiplet made with an older process for low-end CPUs... which might mean smaller cache?
The more important reason this doesn't mean denser caches is that the caches are SRAM not DRAM which are petty much completely different processes. High NA EUV also will likely yield higher density caches, but this is mostly unrelated.
Just a semi-engineer here, not a semi-conductor engineer, but probably not. L1-L3 are on the die, so you'd just be making those at the same time as the rest of your CPU die, so they'll be made with the same process as that is. Which, once that process is the high NA UV, means yes, denser L1-L3. Though I wouldn't be too surprised to see an L3/L4 chiplet made with an older process for low-end CPUs... which might mean smaller cache?