> The current flash architecture is, from a building blocks perspective, identical to dynamic RAM architecture.
This is true of typical NOR flash, but not NAND flash. The smallest word you can read from typical, modern NAND is 8kB. This is not a feature of the controller, but of the way the bit array is laid out. While you could build this memory bus out of NOR, it would be quite expensive -- NAND is not only much more dense, but because it's a commodity with a lot of competition, cost per mm^2 is also much lower than NOR.
This is true of typical NOR flash, but not NAND flash. The smallest word you can read from typical, modern NAND is 8kB. This is not a feature of the controller, but of the way the bit array is laid out. While you could build this memory bus out of NOR, it would be quite expensive -- NAND is not only much more dense, but because it's a commodity with a lot of competition, cost per mm^2 is also much lower than NOR.